Modem electronic circuit design in general, and application specific integrated circuit (ASIC) design in particular, typically begins with a circuit designer writing a high level code that represents the desired functionality of the circuitry. This high level code is typically written in a programming language such as VERILOG.RTM. (VERILOG.RTM. is a registered trademark of Cadence Design System Corp.), VHDL, (very high speed integrated circuit hardware description language), or C language. After the design has been through several iterations and exhibits a degree of stability, the high level description language code can be converted to logic level, which uses gate level logic such as NAND gates and NOR gates etc., to implement the desired functionality described in the aforementioned high level code. The tool that performs this conversion is known as a synthesis tool. Several available synthesis tools can perform this conversion. For example, a software package available from SynOpSys Inc., of 700 East Middlefield Road, Mountain View, Calif., can perform the conversion from high level code to logic level code. As is known to those skilled in the art, the high level code is referred to as register transfer language (RTL) netlist and the logic level code is known as the gate level netlist.
Once the high level code is converted to gate level code, the designer will typically perform additional testing via simulation and formal verification in order to verify that the logic level code is an accurate representation of the high level code. If the logic level code is successfully verified, the logic level code is converted to a detailed layout of the circuit and the circuit is fabricated.
Typically, a formal verification tool in the form of a software product, available from, for example, Chrysalis Symbolic Design, Inc., of 101 Billerica Avenue, North Billerica Mass. is used to compare the high level code (RTL netlist) to the logic level code (gate level netlist) to determine whether they are equivalent. Typically, the RTL netlist is compared to the gate level netlist.
Sometimes during the verification operation, the high level code is changed to implement design changes or revisions. If the change is significant (e.g., a full metal mask change), another gate level netlist is typically generated and another round of verification testing is performed to compare the revised high level code to the revised gate level code.
If a required change to the high level code is minor (e.g., a simple metal mask change) a simplified compiler operation may be performed, thus reducing cost and minimizing production delay. An ECO (engineering change order) compiler is available from for example, SynOpSys Inc. in the form of an ECO compiler. Unfortunately, the cost of the ECO complier is approximately the same as the cost of performing the original formal verification. This indicates that even for a small revision in the high level code, a designer must perform the compile operation and then perform the design verification operation, each operation adding cost and production delay. A shortcoming with this process is that the circuit designer must determine the gate level change corresponding to the high level code change using different and often incompatible tools, or do it purely manually, which is highly error prone. The designer must then perform the verification operation again to verify the equivalency of the revised gate level netlist to the revised RTL netlist.
Unfortunately, the above mentioned verification operation cannot determine the change required to the first gate level netlist to make it match the revised RTL netlist. This predicament requires that the circuit designer switch between the synthesis tool and the verification tool.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.